1. Field of the Invention
The present invention relates to the field of frequency dividers for digital electronic circuits.
2. Description of the Related Art
In many of today's complex computer systems, logic circuits often require their own unique clock frequencies. In order to provide these individual clocking frequencies to the logic circuits, separate crystal oscillators tuned to specific frequencies must be included on the circuit boards. Crystal oscillators require special isolation, including the proximate placement of a substantial number of capacitors to ensure that the waveform of the clock signal is clean. In order to accommodate all of the required crystal oscillators, a large percentage of the computer circuit board would have to be set aside for clock generation. In some cases, where the unique clock frequencies are binarily proportional to the input clock frequency, the unique clock frequencies can be derived from simple binary dividers which are attached to the input clock signals. In many cases, the binary relationships between the input clock frequency and the unique clock frequencies required by the individual circuits do not exist. Thus, in order to achieve these unique clock rates, a complex divider circuit is used to extract the unique frequencies from the input clock frequency. The amount of space on the circuit board required to implement a complex divider circuit may be considerably larger than the space required to isolate a unique crystal oscillator from the remainder of the system.
A few types of analog circuits can be used to divide the input clock signal by a fractional number to achieve a unique clock frequency. For example, a phase lock loop can be used to divide an input signal frequency by a fractional value such as 1.5. The analog phase lock loop is typically a very large circuit and is not easily integrated into large scale integrated circuits (LSI) or into application specific integrated circuits (ASIC) technologies which are presently used in a substantial number of new computer systems. This type of analog circuit generally is undesirable as it requires a large amount of real estate on a circuit board, and, furthermore, very few manufacturers can produce an ASIC with both digital and analog capabilities.
Another example of an attempt to provide a fractional divide-by frequency circuit utilizes a differentiator or a one-shot. In an exemplary divide-by 1.5 circuit, a one-shot is used to increase the frequency of the input signal by two. Next, the doubled frequency signal is applied to a modulo divide-by 3 counter which results in an output signal which is equivalent to the frequency of the input signal divided by 1.5. Systems which use a differentiator or a one-shot are very temperature sensitive. Further, some one-shots are unreliable beyond limited frequency ranges. Therefore, a need exists for a digitally implementable fractional divideby circuit that is frequency and temperature independent and that will enable the user to generate a desired clock frequency from a single input frequency. A further need exists for a simple digital clock divider circuit that can obtain clock speeds which are related to the available clock rates by a non-binarily related value, such as by a fractional value.